1. Field of the Invention
The present invention relates to a digital signal processing apparatus, more particularly relates to a two-dimensional discrete cosine transformation (DCT) system, a two-dimensional inverse discrete cosine transformation (IDCT) system, and a method of processing using the same.
2. Description of the Related Art
In recent years, systems using two-dimensional DCT and two-dimensional IDCT have become the mainstream systems in the field of image compression. Two-dimensional 8.times.8 DOT and two-dimensional 8.times.8 IDCT are expressed by the following equation 1. EQU [C]=(1/4) [N][X][N.sup.t ] (1)
where,
[X] is an input data matrix, and PA1 [C] is an output data matrix. PA1 IDCT: [X]=(1/4) [N.sup.t ][C][N] PA1 [C] is an input data matrix, and PA1 [X] is an output data matrix.
where,
In equation 1, the superscript ".sup.t " indicates a transpose matrix. Therefore, [N.sup.t ] and [N] are transpose matrices of each other.
In equation 1, [X] denotes for example 8.times.8 real (time) domain image matrix data, [C] denotes 8.times.8 frequency domain matrix data corresponding to [X], and [N] denotes a 8.times.8 constant data matrix for transforming [C] to [x].
The constant data matrix [N] can be expressed by the following equation 2 and the transpose matrix [N.sup.t ] by the following equation 3: ##EQU1##
where, ai=cos (i.times..pi./16) i=1.about.7 ##EQU2##
where, ai=cos (i.times..pi./16) i=1.about.7
If a two-dimensional 8.times.8 DCT or IDCT calculation is performed by just simply calculating equation 1, the number of multiplication operations becomes extremely great and it suffers from the disadvantages of a massive amount of hardware including a large number of multipliers becomes necessary.
To overcome this disadvantage, the assignee of this application disclosed in Japanese Patent Publication (Kokai) No.6(1994)-35952, a two-dimensional 8.times.8 DCT system able to reduce the number of multiplication operations in the DCT by dissolving the constant data matrix [N] shown in equation 1 into a matrix [W] of a diagonal component of irrational numbers and other components of all "0" and a matrix [M] of components of irrational numbers, "+1", or "-1", dissolving the constant data matrix [N.sup.t ] into a matrix [W.sup.t ] of the transpose matrix of the above matrix [W] and matrix [M.sup.t ] of the transpose matrix of the matrix [M], and performing the calculation based on these dissolved determinants.
With this two-dimensional 8.times.8 DCT system, it was possible to transform the DCT equation expressed by equation 1 to equation 4 and calculate equation 4 by a routine of the following steps S1 to S3 so as to reduce the number of multiplication operations and therefore keep down the increase in size of computation circuits caused by an increase in the number of multipliers. ##EQU3##
The matrix [W] in equation 4 can be expressed by the following equation 6: ##EQU4##
where, a.sub.i =cos (i.times..pi./16), i=1 to 7
The matrix [M] in equation 4 can be expressed by the following equation 7: ##EQU5##
where, ai=cos (i.times..pi./16) i=1.about.7
Further, the matrix [W.sup.t ] and matrix [M.sup.t ] in equation 4 are transpose matrices of the matrix [W] and matrix [M] and can be expressed by the following equations 8 and 9: ##EQU6##
where, ai=cos (i.times..pi./16) i=1.about.7 ##EQU7##
where, ai=cos (i.times..pi./16) i=1.about.7
FIG. 1 is a view of the configuration of a two-dimensional 8.times.8 DCT system (apparatus) 100 for performing the calculation of equation 4.
As shown in FIG. 1, the two-dimensional 8.times.8 DCT system 100 is comprised of a serial/parallel converter 121, a calculation circuit 122, a rearrangement circuit 123, a calculation circuit 124, a parallel/serial converter 125, and a multiplier 126.
In the two-dimensional 8.times.8 DCT system 100, the image data, that is, the matrix [X], is received serially, the matrix [X] is converted to parallel data by the serial/parallel converter 121, the calculation circuit 122 is used to calculate step S1, the rearrangement circuit 123 and calculation circuit 124 are used to calculate step S2, the parallel/serial converter 125 is used to convert the parallel data from the calculation circuit 124 to serial data, the multiplier 126 is used to calculate step S3, and the matrix [C] in the frequency domain is output serially from the multiplier 126.
FIG. 2 is a view of the configuration of the calculation circuit 122.
The xx0 to xx7 shown in FIG. 2 are constituent elements of the vector [xx] shown by the following equation 10. The vector [xx] is comprised by the constituent elements of the row direction of the matrix [X] of equation 4. Further, yy0 to yy7 are the constituent elements of the vector [yy] shown by the following equation 11. The vector [yy] is comprised by the constituent elements of the row direction of the matrix [Y] of step S1. ##EQU8##
The calculation circuit 122 receives as parallel input the 8 elements of input data (xx0, xx1, . . . , xx7) and outputs as parallel output the eight elements of output data (yy0, yy1, . . . , yy7).
In the calculation circuit 122, for example, the input data xx0 is added with the input data xx7 by an adder 90a. The result of the addition operation is output as xp0 to an adder 90b. At the adder 90b, xp0 and xp2 are added. The result of the addition operation is output as xr0 to the adder 90c. At the adder 90c, xr0 and xr1 are added. The result of the addition operation is output as yy0.
FIG. 3 is a view of the configuration of the serial/parallel converter 121.
In the serial/parallel converter 121, when data is input from an input terminal serially at a rate of one word every cycle, eight data are held at the registers (unit delay circuits) REG0 to REG7 after the end of 8 cycles, so these are transferred to the corresponding eight hold circuits HOLD0 to HOLD7. By obtaining the outputs from the hold circuits HOLD0 to HOLD7 from the output terminals of the same, 1-input, 8-output serial-to-parallel conversion is achieved.
FIG. 4 is a view of the configuration of the parallel/serial converter 125.
In the parallel/serial converter 125, eight data are input from eight input terminals in one cycle. The data are held in the registers REG8 to REG15 through the eight selectors SEL0 to SEL7. The selectors SEL0 to SEL7 are controlled by control signals from a control circuit, not shown, so that the registers REG8 to REG15 are connected in series at cycle 2 on. The data are output one word at a time from the output terminals over 8 cycles, so 8-input, 1-output parallel/serial conversion is achieved.
The hold circuits hold the data and basically are the same as registers. Accordingly, in the calculation circuit 100 of FIG. 1, 16 hold circuits are required in the serial/parallel converter 121 and eight in the parallel/serial converter 125, for a total of 24.
In the earlier filed Japanese patent application mentioned earlier, further, disclosure was made of a two-dimensional 8.times.8 IDCT system able to reduce the number of multiplication operations in the IDCT by dissolving the constant data matrix [N] shown in equation 1 into a matrix [G] of a diagonal component of irrational numbers and other components of all "0" and a matrix [F] of components of irrational numbers, "+1", or "-1", dissolving the constant data matrix [N.sup.t ] into a matrix [G.sup.t ] of the transpose matrix of the above matrix [G] and a matrix [F.sup.t ] of the transpose matrix of the matrix [F], and performing the calculation based on these dissolved determinants.
With this two-dimensional 8.times.8 IDCT system, it was possible to transform the IDCT equation shown in equation 1 to equation 12 and calculate the following equation 12 by a routine of the following steps S1' to S3' so as to reduce the number of multiplication operations and therefore keep down the increase in size of computation circuits caused by an increase in the number of multipliers. ##EQU9##
The matrix [G] in equation 12 can be expressed by the following equation 14: ##EQU10##
where, AAi=1/{2.times.cos (i.times..pi./16)} i=1.about.7
The matrix [F] in equation 12 can be expressed by the following equation 15: ##EQU11##
where, Uhk=2.times.cos (h.times..pi./16).times.cos (k.times..pi./16)
Further, the matrix [G.sup.t ] and matrix [F.sup.t ] in equation 12 are transpose matrices of the matrix [G] and matrix [F] and can be expressed by the following equations 16 and 17: ##EQU12##
where, AAi=1/{2.times.cos (i.times..pi./16)} i=1.about.7 ##EQU13##
where, Uhk=2.times.cos (h.times..pi./16).times.cos (k.times..pi./16)
FIG. 5 is a view of the configuration of a conventional two-dimensional 8.times.8 IDCT system for performing the calculation of equation 12.
As shown in FIG. 5, the two-dimensional 8.times.8 IDCT system 130 is comprised of a multiplier 131, a serial/parallel converter 121, a calculation circuit 133, a rearrangement circuit 134, a calculation circuit 135, and a parallel/serial converter 125.
In the two-dimensional 8.times.8 IDCT system 130, the frequency domain data, that is, the matrix [C], is received serially as input, the calculation of step S1' is performed serially at the multiplier 131, the result is converted to parallel data by the serial/parallel converter 121, the calculation circuit 133 is used to calculate step S2', the rearrangement circuit 134 and calculation circuit 135 are used to calculate step S3', the parallel/serial converter 125 is used to convert the parallel data from the calculation circuit 135 to serial data, and real domain image data, that is, the matrix [X], is output serially.
FIG. 6 is a view of the configuration of the calculation circuit 135.
The vector [yy] shown in FIG. 6 is expressed by equation 18 and the vector [xx] by equation 19. The vector [yy] is a vector comprised by the constituent elements of the row direction of the matrix obtained by rearranging by the rearrangement circuit 134 the rows and columns of the matrix [Q] produced at step S2'. The vector [xx] is a vector comprised of the constituent elements in the row direction of the real domain matrix [X] produced at step S3'. ##EQU14##
The calculation circuit 135 shown in FIG. 6 receives as parallel input the eight elements of input data (yy0, yy1, . . . , yy7) and outputs as parallel output the eight elements of output data (xx0, xx1, . . . , xx7).
In this two-dimensional 8.times.8 IDCT system 130 as well, in the same way as the two-dimensional 8.times.8 DCT system 100, a total of 24 registers is required in the serial/parallel converter 121 and parallel/serial converter 125.
In the two-dimensional 8.times.8 DCT system 100 and two-dimensional 8.times.8 IDCT system 130 of the related art, it was possible to reduce the number of multipliers and thereby the size of the circuit compared with the prior art by calculation of the routines of steps S1 to S3 and steps S1' to S3', but when inputting and outputting matrix data serially word by word, a serial/parallel converter 121 and parallel/serial converter 125 including a large number of registers became necessary like in the past as shown by FIGS. 1 and FIG. 5, so there was the problem that the size of that portion of the circuit ended up becoming larger.